(Updated) Upcoming Hardware Launches 2018

INTRODUCTION

In this article, which our group will consistently refresh, we will keep up a developing rundown of data relating to up and coming equipment discharges dependent on holes and authority declarations as we spot them. There will clearly be a huge amount of gossipy tidbits on unreleased equipment, and it is our objective to—in light of our long stretches of industry encounter—bar the insane ones. Notwithstanding these forthcoming equipment discharge news, we will frequently modify the structure of this article to all the more likely sort out data. Each time a critical change is made to this article, it will re-show up on our first page with "another" pennant, and the augmentations will be archived in the gathering remarks string. This article won't spill data we marked a NDA for. 

Don't hesitate to impart your insights and tips in the discussion remarks string.

PROCESSORS

AMD Zen 2 [updated]

• Release Date: sample in 2018, launch in 2019
• 7 nm production process at TSMC
• 7 nm brings 2x density, 1/2 power (at same performance), or 1.25x performance (at same power)
• Claims better performance/watt than Intel 10 nm
• Floating point unit doubled to 256-bit
• EPYC SKUs come with up to 64 cores, using four to eight 7 nm CPU dies (each has 8 cores)
• The CPU dies are connected to a central IO die, which is still made on 14 nm
• Adds support for PCI-Express 4.0 (128 lanes total: 96-lanes on EPYC from the CPU + 32 from the Southbridge)
• EPYC parts use an 8-channel DDR4 memory interface
• Major update to the microarchitecture, including IPC improvements
• New front end with improved branch-predictor, faster instruction prefetch, large L1 and L2 cache
• Codename: Matisse (CPU), Picasso (APU w/ IGP)
• Hardening against Meltdown/Spectre (through architecture)
• Adds new instructions: Cache Line Write Back (CLWB), Read Processor ID (RDPID), and Write Back and Do Not Invalidate Cache (WBNOINVD)
• 13% IPC gain over Zen+, 16% over Zen 1
• Continues to use socket AM4
• Tape-out: end of 2018

New 28-core HEDT platform derived from LGA3467

• Released as Xeon W-3175X
• Client-segment implementation of the Skylake XCC die
• No STIM
• Up to 28 cores: 16-core, 24-core, 26-core, and 28-core SKUs possible
• Six-channel DDR4 Memory interface, Up to 768 GB non-ECC memory
• Uses new X599 chipset, new motherboards required
• 48 PCIe gen 3.0 lanes
• Two AVX-512 FMA Units
• Confirmed Motherboard: ASUS ROG Dominus Extreme

GRAPHIC CARDS

NVIDIA GeForce RTX 2070 Ti [updated]

• Gigabyte (where "2070 Ti" originated from), now claims that this was just a typo
• Release Date: Unknown
• Based on Turing TU104 (same as RTX 2080)
• Faster than GTX 1070 Ti and GTX 1080
• Pricing $600-650 (ie, half of RTX 2080 Ti)

NVIDIA GeForce 2060 & 2050

• Release Date: Probably 2019
• GeForce 2060 based on cut down TU106
• GeForce 2050 based on new, smaller, chip
• Might not include support for RTX

NVIDIA Volta

• Architecture launched with $3000 Titan V
• Seems to be a dead end, now with Turing being the newer architecture and already released

NVIDIA Ampere

• Release Date: 2018
• Possibly scrapped due to end of mining boom

NVIDIA Turing Mobile / RTX 20-Series Mobility

• Release Date: Q1 2019
• GeForce RTX 2080 Mobility Max-Q, based on TU104M
• GeForce RTX 2070 Mobility Max-Q
• GeForce RTX 2060 Ti Mobility
• GeForce RTX 2060 Mobility
• GeForce RTX 2050 Ti Mobility
• GeForce RTX 2050 Mobility

AMD Polaris 30 / RX 590 [updated]

• Release Date: Q4 2018
• Only one SKU expected: Radeon RX 590
• New shrink of Polaris 20 to TSMC's 12 nanometer production process
• 15% performance gains

MEMORY

DDR5 System Memory

• Release Date: Late 2019/2020
• JEDEC standard not fully complete yet, expected for summer 2018
• Demo'd in May 2018 by Micron: DDR5-4400
• Samsung 16 Gb DDR5 DRAM developed since February 2018
• Samsung has completed functional testing and validation of a LPDDR5 prototype: 10 nm class, 8 Gbit, final clocks: DDR5-5500 and DDR5-6400
• 4800 - 6400 Mbps
• Expected to be produced using 7 nm technologies
• 64-bit link at 1.1 V
• Voltage regulators on the DIMM modules

HBM3 Graphics Memory

• Release Date: Not before 2019
• Double the memory bandwidth per stack (4000 Gbps expected)
• Expected to be produced using 7 nm technologies

OTHERS

QLC NAND Flash [launched]

• QLC has launched on Intel 660p and Crucial P1, drives expected from Samsung soon
• Significant cost reduction for SSDs (around 30% expected)
• Stores four-bits per cell instead of three (TLC), two (MLC), one (SLC).
• Drives up to 8 TB in capacity
• Lower endurance (~ 1000 P/E cycles) and slower writes
• Intel: 660p using QLC flash announced on August 6th: NVMe PCIe x4, 64-layer 3D QLC, SMI 2263 controller, 512 GB ($100), 1 TB ($200), 2 TB ($400)
• Samsung: mass production started: 1 Tbit QLC NAND chips, Capacities: 1 TB, 2 TB and 4 TB, NVMe M.2 for enterprise planned
• Micron: first SSDs available now, QLC uses 64-layer 3D NAND
• Western Digital: 96-layer, 1.33 Tb per chip, developed in partnership with Toshiba, sampling since Q3 2018
• Toshiba: mass production late 2018, early 2019. 96-layers, 1.33 Tbit per chip

Hynix 4D NAND [updated]

• Release Date: H1 2019
• Developed by SK Hynix
• Sampling in Q4 2018
• Reduces chip physical size, while increasing capacity at the same time
• Supports TLC and QLC
• 30% higher write and 25% higher read performance
• 1.2 V
• 1st generation: 96 stacks, 1.2 Gbps per pin, 512 Gbit TLC
• 128 stacks in development, scales up to 512 stacks

Toshiba XL-Flash

• Developed by Toshiba
• Uses existing SLC flash technology to improve latencies
• 1/10th the read latency of TLC
• Good for random IOPS and better QoS at shallow queue depth
• Can combine SLC and TLC/QLC for tiered, cost-optimized storage
• Intel Optane memory competitor

PCI-Express 4.0 [updated]

• Specification released in late 2017
• 16 GT/s bandwidth per lane, per direction (2x the bandwidth of PCIe 3.0)
• Reduced latency
• Lane margining
• I/O virtualization capabilities
• Will be supported by AMD Zen 2 and Vega 20 (Radeon Instinct MI60 & MI50)

PCI-Express 5.0

• Release Date: Q1 2019
• 32 GT/s bandwidth per lane, per direction (4x the bandwidth of PCIe 3.0)
• 128/130 bit encoding (= 1.5% overhead)
• Physical connector targeted to be backward compatible